1. Field of the Invention
The present invention relates to memory cells and, more particularly, to a multi-state electromechanical memory cell.
2. Description of the Related Art
Memory cells are embedded in most current-generation electronic devices, such as computers, cell phones, cameras, and games. The push and motivation in the memory industry is to shrink the size of the cells so that more cells can be packed in a given area, while maintaining the data retention and endurance attributes of the cells.
Memory cells are commonly classified as either volatile or non-volatile memory cells. A volatile memory cell stores data only as long as power is provided to the memory cell. A non-volatile memory cell, on the other hand, continues to retain data long after power has been removed from the memory cell.
Conventional non-volatile memory cells, such as EPROM, EEPROM, and FLASH cells, are transistor-based cells that utilize a floating gate to store data in the cell. The presence of a charge on the floating gate indicates a first logic state, while the absence of a charge on the floating gate indicates a second logic state.
Recently, non-volatile memory cells have been developed using micro-electromechanical (MEMS) technology. MEMS-based memories utilize the position of a mechanical member to store data in the memory cell. When the mechanical member is in a first position that is spaced away from an electrode, the memory cell exhibits a first electrical property that indicates a first logic state. On the other hand, when the mechanical member is in a second position that contacts the electrode, the memory cell exhibits a second electrical property that indicates a second logic state.
FIGS. 1A-1B show cross-sectional views that illustrate a prior-art MEMS-based memory cell 100. As shown in FIG. 1A, cell 100 includes a non-conductive region 110, and a first conductive strip 112 that contacts the top surface of non-conductive region 110. In addition, cell 100 includes a second conductive strip 114 that contacts the top surface of non-conductive region 110, and a conductive cantilever member 116 that contacts second conductive strip 114, and extends out over first conductive strip 112.
In operation, memory cell 100 is programmed by applying a program voltage to first conductive strip 112, and ground to cantilever member 116 via second conductive strip 114 (or visa versa). The difference between the program voltage and ground generates an electrostatic force that pulls the end section of cantilever member 116 down to contact conductive strip 112. Further, after the programming voltages have been removed, cantilever member 116 remains stuck to conductive strip 112 due to the surface adhesion forces between conductive strip 112 and the end section of cantilever member 116.
Memory cell 100 is read using a sense circuit that determines whether a voltage on conductive strip 112 is also present on cantilever member 116. Alternately, the sense circuit can read memory cell 100 by determining whether a current can flow from conductive strip 112 to cantilever member 116.
As shown in FIG. 1A, before being programmed, cantilever member 116 is in a first position that is spaced apart from conductive strip 112. In this position, the sense circuit determines that conductive strip 112 and cantilever member 116 have different voltages or, alternately, that a current can not flow from conductive strip 112 to cantilever member 116. As a result, the sense circuit indicates that memory cell 100 has not been programmed.
As shown in FIG. 1B, after being programmed, cantilever member 116 is in a second position that contacts conductive strip 112. In this position, the sense circuit determines that conductive strip 112 and cantilever member 116 have the same voltage or, alternately, that a current can flow from conductive strip 112 to cantilever member 116. As a result, the sense circuit indicates that memory cell 100 has been programmed.
One of the problems with memory cell 100 is that it is not possible to erase memory cell 100 so that cantilever member 116 is again spaced apart from conductive strip 112. If memory cell 100 can not be erased so that cantilever member 116 is again spaced apart from conductive strip 112, then memory cell 100 is limited to one-time programmable applications.
Memory cell 100 can be converted into a triple-state memory cell by the addition of an overlying conductive electrode that lies a distance vertically above cantilever 116. A triple-state memory cell has three possible states, depending on the position of a movable member (i.e., cantilever 116).
FIGS. 1AA-1CC show cross-sectional views that illustrate a prior-art triple-state memory cell 150. Triple-state memory cell 150 is similar to memory cell 100 and, as a result, utilizes the same reference numerals to designate the structures which are common to both memory cells. As shown in FIGS. 1AA-1CC, memory cell 150 differs from memory cell 100 in that memory cell 150 also has a structural member 152 and a third conductive strip 154 that contacts non-conductive region 110. In addition, memory cell 150 has a conductive via 156 that contacts conductive strip 154, and a conductive electrode 158 that contacts structural member 152 and conductive via 156 to lie above cantilever 116.
In triple-state memory cell 150, the first state is state 0 which corresponds with the initial position of cantilever 116 as shown in FIG. 1AA. The initial position of cantilever 116 is the position of cantilever 116 when no external force has yet been applied to cantilever 116 and memory cell 150 has never been programmed.
The second state is state +1 which corresponds with cantilever 116 being pulled down to contact conductive strip 112 as shown in FIG. 1BB. Cantilever 116 is pulled down from the initial position shown in FIG. 1AA to contact conductive strip 112 in the same manner as described above with respect to memory cell 100.
The third state is state −1 which corresponds with cantilever 116 being pulled up to contact conductive electrode 158 as shown in FIG. 1CC. Cantilever 116 is pulled up from the initial position shown in FIG. 1AA to contact conductive electrode 158 in the same manner that cantilever 116 is pulled down except that the program voltages are applied to cantilever 116 and conductive electrode 158 rather than conductive strip 112 and cantilever 116.
Cantilever 116 can also be moved from state +1 to state −1 or from state −1 to state +1. For example, to move cantilever 116 from state −1 to state +1, a reprogram voltage is applied to first conductive strip 112, while ground is applied to cantilever member 116 and conductive electrode 158. The difference between the reprogram voltage and ground generates an electrostatic force that pulls the end section of cantilever member 116 away from conductive electrode 158 down to contact conductive strip 112. After the reprogramming voltages have been removed, cantilever member 116 remains stuck to conductive strip 112 due to the surface adhesion forces.
One problem with moving cantilever 116 from one non-initial state to another non-initial state (i.e., state −1 to state +1) is that the required reprogram voltage is very high. Once cantilever 116 is in contact with conductive strip 112 or conductive electrode 158, the surface adhesion forces are quite strong.
Thus, the reprogram voltage must be substantially larger than the program voltage. As a result, the movement of cantilever 116 from one non-initial state to another non-initial state requires very high voltage circuitry which, in turn, increases the complexity of memory cell 150 and the fabrication process.
FIGS. 2A-2B show cross-sectional views that illustrate another prior-art MEMS-based memory cell 200. As shown in FIG. 2A, memory cell 200 includes a non-conductive region 210 that includes an opening, and a conductive member 212 that lies in the opening. As further shown in FIG. 2A, the top surface of conductive member 212 lies below the top surface of non-conductive region 210. In addition, cell 200 includes a conductive strip 214 that contacts the top surface of non-conductive region 210, and extends over conductive member 212.
In operation, memory cell 200 is programmed in the same way that memory cell 100 is programmed. With memory cell 200, a program voltage is applied to conductive member 212, and ground is applied to conductive strip 214 (or visa versa). In this case, the difference between the program voltage and ground generates an electrostatic force that pulls the center section of conductive strip 214 down to contact conductive member 212. Further, after the programming voltages have been removed, conductive strip 214 remains stuck to conductive region 212 due to the surface adhesion forces between conductive region 212 and the center section of conductive strip 214.
Memory cell 200 is also read in the same way that memory cell 100 is read. In this case, a sense circuit determines whether a voltage on conductive member 212 is also present on strip 214. Alternately, the sense circuit can read memory cell 200 by determining whether a current can flow from conductive member 212 to conductive strip 214.
As shown in FIG. 2A, before being programmed, conductive strip 214 is in a first position that is spaced apart from conductive member 212. In this position, the sense circuit determines that conductive member 212 and conductive strip 214 have different voltages or, alternately, that a current can not flow from conductive member 212 to conductive strip 214. As a result, the sense circuit indicates that memory cell 200 has not been programmed.
As shown in FIG. 2B, after being programmed, conductive strip 214 is in a second position that contacts conductive member 212. In this position, the sense circuit determines that conductive member 212 and conductive strip 214 have the same voltage or, alternately, that a current can flow from conductive member 212 to conductive strip 214. As a result, the sense circuit indicates that memory cell 200 has been programmed.
However, like memory cell 100, once programmed, it is not possible to erase memory cell 200 so that conductive strip 214 is again spaced apart from conductive region 212. If memory cell 200 can not be erased so that conductive strip 214 is again spaced apart from conductive member 212, then memory cell 200 is limited to one-time programmable applications.
In addition, like memory cell 100, memory cell 200 can be converted into a triple-state memory cell by the addition of an overlying conductive electrode that lies a distance vertically above conductive strip 214 of memory cell 200. However, a triple-state version of memory cell 200 suffers from the same drawbacks as memory cell 150, namely that a very high reprogram voltage is required to move conductive strip 214 from one non-initial state to another non-initial state (i.e., state +1 to state −1).
One common application of one-time programmable memory cells is to trim a device or circuit to adjust the electrical characteristics of the device or circuit to have a very precise value, often to match the electrical characteristics of another device or circuit. One-time programmable memory cells, however, provide no flexibility.
Thus, in situations where devices or circuits must be individually characterized, conventional memory cells must often be used to identify the trim that provides the most precise value. However, unlike MEMS devices, which are typically formed on the top surface of the interconnect structure, conventional memory cells are fabricated on the silicon surface and, therefore, consume valuable silicon real estate. As a result, there is a need for an electromechanical memory cell which can be programmed more than one time.